1. Field of the Invention
This invention relates to testing of a hardware design. More particularly, this invention relates to verification of address translation mechanisms in a hardware design.
2. Description of the Related Art
Most modern architectures provide a virtual address space for their applications. An operating system maps these virtual addresses to actual hardware resources, such as memory, disk, and I/O ports, using address translation mechanisms. Supporting a separate virtual address space allows the application to be oblivious to the memory organization. The application may ignore actual memory sizes as well as the details of memory allocation by the operating system.
Address translation mechanisms also play a part in memory protection and caching by maintaining related properties for basic translated memory units (e.g., pages or segments). The translation is mostly carried out using hardware mechanisms, such as translation tables and control registers. The operating system maintains these resources through software, but the translation itself is carried out by the hardware.
An ever-growing demand for better performance requires address translation mechanisms to become more complex in new hardware designs, thereby increasing the risk of design flaws or bugs. Indeed, a significant percentage of such design flaws stems, more or less directly, from address translation mechanisms. Moreover, the complexity of these mechanisms causes the flaws to be difficult to find.
Simulation-based techniques, which continue to be a cornerstone of functional verification, are implemented through the running of test cases. In the past, relatively low design complexity enabled exclusive reliance on deterministic tests that were developed manually. Current practices foster the use of automatic random stimuli generators to add quantity and randomness into the process. In order to stress the verified design, and to ensure good test coverage, the generator needs to have knowledge of the properties of a design-under-test.
The need for a test generation solution applicable to various architectures has led to a model-based test generation scheme, in which knowledge about the design-under-test is kept separate from the test generation engine. The generator is partitioned into a generic, architecture-independent engine and a model that describes the design-under-test.
During the past decade, model-based random test program generators have become popular in architectural design verification and software testing. An example of such a random test generator is the IBM tool, “Genesys”, which is disclosed in the document Model-Based Test Generation for Process Design Verification, Y. Lichtenstein et al., in Sixth Innovative Applications of Artificial Intelligence Conference, August 1994, pp. 83–94.
The general approach to random test program generation is further discussed in the documents Test Program Generation for Functional Verification of PowerPC Processors in IBM, A. Aharon, D. Goodman, M. Levinger, Y. Lichtenstein, Y. Malka, C. Metzger, M. Molcho, and G. Shurek, in 32nd Design Automation Conference, pages 279–285, 1995.
Another conventional test generator, AVPGEN, is disclosed in the document AVPGEN—A Generator for Architecture Verification Test Cases, A. Chandra, et al., IEEE Trans. Very Large Scale Integration (VLSI) Syst. 3, No. 2, 188–200 (June 1995).
A test generator, adapted for testing hardware processor design, is disclosed in commonly assigned U.S. Pat. No. 6,006,028, which is herein incorporated by reference. The generator is directed to storing data representing the processor instruction set and modeling semantic entities associated with each instruction in a declarative model or specification.
In U.S. patent application Ser. No. 09/847,309, (Publication No. US 2003/0014734 A1), entitled Technique Using Persistent Foci For Finite State Machine Based Software Test Generation, of common assignee herewith and herein incorporated by reference, an automated method of software testing is disclosed in which a software program is represented as a finite state machine model, and transitions between stages are represented as directed edges between states.
The development and maintenance of test generators such as the above, when targeted at address translation mechanisms, has proved to be difficult and expensive. The model-based approach, including a comprehensive and declarative specification of a design mechanism, has apparently never been successfully applied to the realm of address translation. Instead, for every new processor design that a test generator is required to support, a developer must write code to handle the specific translation mechanism being verified.